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as8e512k8 rev. 2.0 12/99 austin semiconductor, inc. reserves the right to change products or specifications without notice. 1 eeprom as8e512k8 austin semiconductor, inc. general description the austin semiconductor, inc. as8e512k8 is a 4 megabit cmos eeprom module organized as 512k x 8-bits. it is built with four 128k x 8 components and a single decoder. the as8e512k8 achieves high speed access, low power consumption and high reliability by employing advanced cmos memory technology. software data protection is implemented using the jedec optional standard algorithm. this military temperature grade product is ideally suited for military and space applications requiring high reliability. available as military specifications ? smd 5962-93091 ? mil-std-883 features ? access times of 150, 200, 250, and 300 ns ? jedec compatible pinout ? 10,000 write endurance cycles ? 10 year data retention ? organized as 512kx8 ? operation with single 5 volt supply ? low power cmos ? ttl compatible inputs and outputs options marking ? packaging 32 pin 600 mil dip cw no. 112 ? timing 150ns -150 200ns -200 250ns -250 300ns -300 ? operating temperature range -military (-55 o c to +125 o c) xt -industrial (-40 o c to +85 o c) it 512k x 8 eeprom eeprom module pin assignment (top view) 32-pin dip & 32-pin soj (cw) a17 a18 ce\ i/o 0 - i/o 7 oe\ 1 of 4 decoder u1 u4 u2 u3 i/o 0 - i/o 7 i/o 0 - i/o 7 i/o 0 - i/o 7 i/o 0 - i/o 7 a0 - a16 a0 - a16 a0 - a16 we\ a0 - a16 we\ we\ we\ oe\ oe\ oe\ ce\ a0 - a16 ce\ ce\ ce\ we\ oe\ a18 a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o 0 i/o 1 i/o 2 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vcc we\ a17 a14 a13 a8 a9 a11 oe\ a10 ce\ i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 for more products and information please visit our web site at www.austinsemiconductor.com a0 - a18 address inputs i/o 0 - i/o 7 data inputs/outputs ce\ chip select oe\ output enable we\ write enable vcc +5.0v power pin description
as8e512k8 rev. 2.0 12/99 austin semiconductor, inc. reserves the right to change products or specifications without notice. 2 eeprom as8e512k8 austin semiconductor, inc. toggle bit: in addition to data\ polling the as8e512k8 provides another method for determining the end of a write cycle. during the write operation, successive attempts to read data from the device will result in i/o 6 toggling between one and zero. once the write has completed, i/o 6 will stop toggling and valid data will be read. reading the toggle bit may begin at any time during the write cycle. data protection: if precautions are not taken, inadvertent writes may occur during transitions of the host power supply. the e 2 module has incorpo- rated both hardware and software features that will protect the memory against inadvertent writes. hardware protection: hardware features protect against inadvertent writes to the as8e512k8 in the following ways: (a) vcc sense - if vcc is below 3.8v (typical) the write function is inhibited; (b) vcc power-on delay - once vcc has reached 3.8v the device will automatically time out 5ms (typical) before allowing a write; (c) write inhibit - holding any one of oe\ low, ce\ high or we\ high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typical) on the we\ or ce\ inputs will not initiate a write cycle. software data protection: a software controlled data protection feature has been imple- mented on theas8e512k8. when enabled, the software data protec- tion (sdp), will prevent inadvertent writes. the sdp feature may be enabled or disabled by the user and is shipped with sdp disabled, sdp is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to software data protection algorithm). after writing the three byte command sequence and after t wc the entire as8e512k8 will be protected from inadvertent write operations. it should be noted, that once protected the host may still perform a byte of page write to the as8e512k8. this is done by preceding the data to be written by the same three byte command sequence used to enable sdp. once set, sdp will remain active unless the disable command sequence is issued. power transitions do not disable sdp and sdp will protect the as8e512k8 during power-up and power- down conditions. all command sequences must conform to the page write timing specifications. the data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation. after setting sdp, any attempt to write to the device without the three byte command sequence will start the internal write timers. no data will be written to the device; however, for the duration of t wc , read operations will effectively be polling operations. device operation: the as8e512k8 is an electricaly erasable and programmable memory module that is accessed like a static ram for the read or write cycle without the need for external components. the device contains a 128-byte-page register to allow writing of up to 128 bytes of data simultaneously. during a write cycle, the address and 1 to 128 bytes of data are internally latched, freeing the address and data bus for other operations. following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. the end of a write cycle can be detected by data\ polling of i/o7. once the end of a write cycle has been detected a new access for a read or write can begin. read: the as8e512k8 is accessed like a static ram. when c/e\ and oe\ are low and we\ is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state when either ce\ or oe\ is high. this dual-line control gives designers flexibility in preventing bus contention in their system. byte write: a low pulse on the we\ or ce\ input with ce\ or we\ low (respectively) and oe\ high initiates a write cycle. the address is latched on the falling edge of ce\ or we\, whichever occurs last. the data is latched by the first rising edge of ce\ or we\. once a byte, word or double word write has been started it will automatically time itself to completion. page write: the page write operation of the as8e512k8 allows 1 to 128 bwdws of data to be written into the device during a single internal programming period. each new bwdw must be written within 150us (t blc ) of the previous bwdw. if the t blc limit is exceeded the as8e512k8 will cease accepting data and commence the internal programming operation. for each we\ high to low transition during the page write operation, a7-a18 must be the same. the a0-a6 inputs are used to specify which bytes within the page are to be written. the bytes may be loaded in any order and may be altered within the same load period. only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. data\ polling: the as8e512k8 features data\ polling to indicate the end of a write cycle. during a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on i/o 7. once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. data\ polling may begin at anytime during the write cycle.
as8e512k8 rev. 2.0 12/99 austin semiconductor, inc. reserves the right to change products or specifications without notice. 3 eeprom as8e512k8 austin semiconductor, inc. pin capacitance (f= 1mhz, t = 25 c) (1) electrical characteristics and recommended dc operating conditions (-55 o c as8e512k8 rev. 2.0 12/99 austin semiconductor, inc. reserves the right to change products or specifications without notice. 4 eeprom as8e512k8 austin semiconductor, inc. a.c. read waveforms (1,2,3,4) notes: 1. ce\ may be delayed up to t acc -t ce after the address transi- tion without inpact on t acc . 2. oe\ may be delayed up to t ce -t oe after the falling edge of ce\ without inpact on t ce or by t acc -t oe after an address change without inpact on t acc . 3. t df is specified from oe\ or ce\ whichever occurs first (c l = 5pf). 4. this parameter is characterized and is not 100% tested. 5. a17 and a18 must remain valid through the we\ and ce\ low pulse. electrical characteristics and recommended ac read operating conditions (-55 o c

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as8e512k8 rev. 2.0 12/99 austin semiconductor, inc. reserves the right to change products or specifications without notice. 5 eeprom as8e512k8 austin semiconductor, inc. ac write waveforms - ce\ controlled 5 ac write waveforms - we\ controlled 5 electrical characteristics and recommended ac write operating conditions (-55 o c as8e512k8 rev. 2.0 12/99 austin semiconductor, inc. reserves the right to change products or specifications without notice. 6 eeprom as8e512k8 austin semiconductor, inc. v ih v il v h v ih v ih v il ce\ ? oe\ ? we\ t s t w t h page mode write waveforms (1,2,3) chip erase waveforms notes: 1. a7 through a16 must specify the page address during each high to low transition of ? w / e (or ? c / e). 2. ? o / e must be high only when ? w / e and ? c / e are both low. 3. a17 and a18 must remain valid throughout the we\ and ce\ low. page mode characteristics notes: t s = 5 m sec (min) t w = t h = 10 msec (min) v h =12.0 v +/- 0.5 v parameter symbol min max units address, oe\ setup time t as , t oes 10 ns address hold time t ah 50 ns chip select setup time t cs 0ns chip select hold time t ch 0ns write pulse width (we\ or ce\) t wp 100 ns data setup time t ds 50 ns data, oe\ hold time t dh , t oeh 10 ns a0-a18 data t as t wp t ah t wph t dh t ds t blc t wc byte 0 byte 126 byte 127 byte 1 byte 2 byte 3 ? ce\ oe\ we\ valid addr valid data
as8e512k8 rev. 2.0 12/99 austin semiconductor, inc. reserves the right to change products or specifications without notice. 7 eeprom as8e512k8 austin semiconductor, inc. software data protection enable algorithm (1) software data protection disable algorithm (1) notes: 1. data format: i/o 7 - i/o0 (hex) 2. write protect state will be active at end of write even if no other data is loaded. 3. write protect state will be deactivated at end of period even if no other data is loaded. 4. 1 to 128 bytes of data are loaded. load data 55 to address 2aaa writes enabled (2) enter data protect state load data aa to address 5555 load data xx to any address (4) load data a0 to address 5555 load last byte to last address exit data protect state (3) load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 20 to address 5555 load data xx to any address (4) load last byte to last address load data 55 to address 2aaa
as8e512k8 rev. 2.0 12/99 austin semiconductor, inc. reserves the right to change products or specifications without notice. 8 eeprom as8e512k8 austin semiconductor, inc. software protected program cycle waveform (1,2,3,4) notes: 1. a0-a14 must conform to the addressing sequence for the first three bytes as shown above. 2. after the command sequence has been issued and a page write operation follows, the page address inputs (a7-a18) must be the same for each high to low transition of we\ (or ce\). 3. oe\ must be high only when we\ and ce\ are both low. 4. a17 and a18 must remain valid throughout the we\ and ce\ low cycle. oe\ ce\ we\ a0-a6 a7-a18 data t wp t wph t blc t as t ah t ds t dh byte 0 byte 126 byte 127 byte address page address 5555 2aaa 5555 55 a0 aa t wc
as8e512k8 rev. 2.0 12/99 austin semiconductor, inc. reserves the right to change products or specifications without notice. 9 eeprom as8e512k8 austin semiconductor, inc. data polling characteristics (1) notes: 1. these parameters are characterized and not 100% tested. 2. see a.c. read characteristics. data polling waveforms we\ ce\ oe\ t oe high z t oeh t wr an an an an an i/o7 a0-a16 parameter symbol min max units data hold time t dh 10 ns oe\ hold time t oeh 10 ns oe\ to output delay 2 t oe ns write recovery time t wr 0ns
as8e512k8 rev. 2.0 12/99 austin semiconductor, inc. reserves the right to change products or specifications without notice. 10 eeprom as8e512k8 austin semiconductor, inc. notes : 1. toggling either oe\ or ce\ or both oe\ and ce\ will operate toggle bit. 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. toggle bit waveforms (1,2,3) notes: 1. these parameters are characterized and not 100% tested. 2. see a.c. read characteristics. toggle bit characteristics (1) parameter symbol min max units data hold time t dh 10 ns oe\ hold time t oeh 10 ns oe\ to output delay 2 t oe ns oe\ high pulse t oehp 150 write recovery time t wr 0ns t dh t wr t oeh t oe high z we\ ce\ ? oe\ i/o6
as8e512k8 rev. 2.0 12/99 austin semiconductor, inc. reserves the right to change products or specifications without notice. 11 eeprom as8e512k8 austin semiconductor, inc. mechanical definitions* asi case #112 (package designator cw) smd 5962-93091, case outline y d1 d 116 17 32 b1 b min max a 0.161 0.181 a1 0.027 0.047 a2 b 0.009 0.012 b1 0.590 0.610 d 1.654 1.686 d1 0.580 0.600 d2 1.492 1.508 e e1 0.016 0.02 0.100 typ symbol smd specifications 0.125 min *all measurements are in inches. note: these dimensions are per the smd. asi's package dimensional limits may differ, but they will be within the smd limits. a1 e e1 a2 a d2
as8e512k8 rev. 2.0 12/99 austin semiconductor, inc. reserves the right to change products or specifications without notice. 12 eeprom as8e512k8 austin semiconductor, inc. ordering information *available processes it = industrial temperature range -40 o c to +85 o c xt = extended temperature range -55 o c to +125 o c hq = mil-prf-38534 -55 o c to +125 o c device number package type speed ns process as8e512k8 cw -150 /* as8e512k8 cw -200 /* as8e512k8 cw -250 /* as8e512k8 cw -300 /* example: as8e512k8c w-250/xt
as8e512k8 rev. 2.0 12/99 austin semiconductor, inc. reserves the right to change products or specifications without notice. 13 eeprom as8e512k8 austin semiconductor, inc. * asi part number is for reference only. orders received referencing the smd part number will be processed per the smd. asi to dscc part number cross reference* asi package designator cw asi part # smd part # as8e512k8cw-150/hq 5962-9309101hyc as8e512k8cw-150/hq 5962-9309101hya as8e512k8cw-200/hq 5962-9309104hyc as8e512k8cw-200/hq 5962-9309104hya as8e512k8cw-250/hq 5962-9309103hyc as8e512k8cw-250/hq 5962-9309103hya as8e512k8cw-300/hq 5962-9309102hyc as8e512k8cw-300/hq 5962-9309102hya

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